DESIGN VERIFICATION WITH LAB (SYNOPSYS TOOLS)
The Design verification course comprises full-fledged content on System Verilog, UVM, and a project in APB for a deeper understanding of Testbench creation. The course covers the SystemVerilog OOPs, Randomization, Inter-process communication (IPC) and advanced topics on both SV and UVM, providing a solid front on pursuing a career in Design Verification.
Course Instructor:
ChipEdge Learning
₹58528.00
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Course Overview
Schedule of Classes
Course Curriculum
1 Subject
Design Verification with Lab (Synopsys Tools) - D
15 Exercises • 175 Learning Materials
Introduction to Design Verification and System Verilog
Introduction to the ChipEdge Verification Course
Video
00:04:51
ASIC Verification Flow
Video
00:15:10
Levels of Verification and Common Acronyms
Video
00:12:02
Testbench Architecture
Video
00:07:12
Verilog vs SystemVerilog
Video
00:09:51
Upcoming Topics
Video
00:05:24
Quiz 1
Exercise
Module_1_Assignment
PDF
System Verilog Datatypes
Introduction to SV Datatypes
Video
00:13:55
Advantages of SV Datatypes
Video
00:04:22
Logic Datatype
Video
00:03:26
2 State and 4 State Variables
Video
00:08:27
Arrays
Video
00:26:35
Structures and Unions
Video
00:10:23
String Datatypes
Video
00:03:39
Enumerated and Event Datatypes
Video
00:09:08
Quiz 2
Exercise
Module_2 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:27:39
System Verilog Interfaces
Inter module communication using ports vs interfaces
Video
00:08:25
Specific Interface Ports
Video
00:04:55
Referring Interface signals and methods
Video
00:09:22
Interface Process and Methods
Video
00:04:38
Virtual Interface
Video
00:05:07
Clocking Block
Video
00:02:05
Clock Skew and its Declaration
Video
00:06:53
Clocking Blocks as Timing Controls
Video
00:05:01
Quiz 3
Exercise
Module_3 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution Part 1
Video
00:28:35
Lab Solution Part 2
Video
00:16:10
Lab Solution Part 3
Video
00:33:22
System Verilog OOPs
System Verilog and OOPs
Video
00:04:00
System Verilog Class
Video
00:20:03
Inheritance
Video
00:07:41
This and Super Operator
Video
00:05:15
Shallow Copy and Deep Copy
Video
00:16:23
Parameterized and Typedef classes
Video
00:07:10
Polymorphism
Video
00:04:06
Abstract Class
Video
00:07:20
Encapsulation
Video
00:02:09
Dynamic Casting
Video
00:03:23
Scope Resolution Operator
Video
00:05:52
Quiz 4
Exercise
Module_4 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:20:22
Randomization
Directed vs Random Testing
Video
00:09:31
Constrained Random Verification
Video
00:06:23
Randomization Basics
Video
00:17:05
Specifying Constraints
Video
00:27:03
Computing the Solution Space
Video
00:08:07
Constraint Performance Tips
Video
00:04:40
Random Stability
Video
00:04:12
Random Sequences and Case
Video
00:04:14
Quiz 5
Exercise
Module_5 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:24:02
Inter-Process Communication
System Verilog Threads
Video
00:18:02
Event
Video
00:15:02
Mailbox and its Initialization
Video
00:12:09
Parameterized Mailboxes
Video
00:02:29
Mailbox Methods
Video
00:11:57
Introduction to Semaphores
Video
00:04:28
Semaphore Keys
Video
00:07:13
Quiz 6
Exercise
Module_6 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:15:47
Assertions
Verilog and SV Event regions
Video
00:19:33
Program Block
Video
00:08:18
Introduction to Assertions
Video
00:07:22
Advantages of Assertions
Video
00:01:48
Types of Assertions
Video
00:07:49
Sequence and Property
Video
00:03:22
Writing Assertion Sequence Using Operators
Video
00:21:24
Writing Assertion System Tasks
Video
00:07:28
SVA Tips
Video
00:04:57
Quiz 7
Exercise
Module_7 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:29:32
Coverage
Introduction To Coverage
Video
00:14:09
Code Coverage
Video
00:06:38
Functional Coverage
Video
00:23:39
SV for Functional Coverage
Video
00:04:36
Cover Groups & Cover Points
Video
00:09:38
Cover Bins & Cross Coverage Constructs
Video
00:22:55
Coverage Options & Methods
Video
00:12:16
SV Additional Topics
Video
00:09:17
Quiz 8
Exercise
Module_8 Assignment
PDF
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution
Video
00:39:54
Introduction to UVM
Limitation of SV Testbench
Video
00:19:09
Evolution of UVM
Video
00:08:41
Features of UVM
Video
00:18:30
UVM Class Hierarchy
Video
00:12:58
Factory registration UVM Phase TLM RAL
Video
00:10:50
Quiz 9
Exercise
Module_9 Assignment
PDF
UVM Phases
Motivation for Phases in UVM
Video
00:09:45
UVM Phases Categorization
Video
00:07:02
Built Time Phases
Video
00:23:33
Run Time Phases
Video
00:35:38
Clean Up Phases
Video
00:08:07
Reporting Mechanism
Video
00:33:12
Quiz
Exercise
Module_10 Assignment
PDF
UVM -Transaction Level Modelling
Introduction to TLM
Video
00:21:20
Ports Exports Implementation
Video
00:37:48
Analysis Ports
Video
00:14:57
TLM FIFO
Video
00:11:35
Hierarchical Connections
Video
00:14:45
Example of TLM Connections
Video
00:19:10
TLM Implementation Ports Declaration Macros
Video
00:06:55
TLM 2 0
Video
00:10:40
Quiz 10
Exercise
Module_11 Assignment
PDF
UVM - Factory Registration and Methods
Introduction to Factory
Video
00:09:41
Factory Registration
Video
00:04:56
UVM Field Macros
Video
00:12:14
Factory Methods
Video
00:24:26
Create Methods
Video
00:11:27
Factory Override
Video
00:41:43
Quiz 11
Exercise
Module_12 Assignment
PDF
UVM - Construction of Universal Verification Components
Virtual Interface
Video
00:09:21
UVM Config & Resource Database
Video
00:57:55
Construction of UVC
Video
00:58:47
Generating Sequences
Video
00:34:25
Sequence Drive Communication
Video
00:18:36
Quiz 12
Exercise
Module_13 Assignment
PDF
UVM - Register Abstraction Layer (RAL)
Introduction to RAL
Video
00:20:53
Register Model Building Block Classes
Video
01:09:55
Register Model in UVM Env
Video
00:42:33
Access API
Video
00:13:20
Frontdoor and Backdoor Access
Video
00:53:13
Quiz 13
Exercise
Module_14 Assignment
PDF
UVM - Advanced Concepts
Virtual Sequence and Virtual Sequencer
Video
01:05:15
UVM Callbacks
Video
00:26:53
UVM Event
Video
00:08:03
UVM Barrier
Video
00:19:09
UVM Heartbeat
Video
00:25:00
Commonly used Command line Switches
Video
00:12:05
Quiz 14
Exercise
Module_15 Assignment
PDF
Universal Verification Methodology (UVM) - Lab
Lab Guide
PDF
Lab Assignment
PDF
Lab Solution - Part 1
Video
00:30:21
Lab Solution - Part 2
Video
00:48:19
Advanced Peripheral Bus protocol (APB)
APB Protocol
Video
00:48:21
SV Solution Part I
Video
00:20:55
SV Solution Part II
Video
00:50:14
UVM Solution Part I
Video
00:20:05
UVM Solution Part II
Video
00:46:41
UVM Solution Part III
Video
00:33:09
APB Lab Manual - SV
PDF
APB Lab Manual -UVM
PDF
Advanced eXtensible Interface(AXI) 4-Lite
AXI4 LITE
Video
01:09:00
Part 1
Video
00:20:38
Part 2
Video
00:55:55
Part 3
Video
00:51:41
Part 4
Video
00:23:56
Part 5
Video
00:35:13
Lab Manuals
Verilog_command_reference_Manual
PDF
Verilog_Lab1_Manual
PDF
Verilog_Lab2_Manual
PDF
Module 1 System Verilog Data Types Lab Manual
PDF
Module 2 Interfaces Lab Manual
PDF
Module 3 System Verilog OOPS Lab Manual
PDF
Module 4 Randomization Lab Manual
PDF
Module 5 Interprocess Communication Lab Manual
PDF
Module 6 Assertion Lab Manual
PDF
Module 7 Coverage Lab Manual
PDF
APB Lab Manual - SV
PDF
UVM Lab Manuals
PDF
APB Lab Manual -UVM
PDF
Course Instructor
ChipEdge Learning
98 Courses • 900 Students
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