Course Overview
Schedule of Classes
Start Date & End Date
Jan 17 2025 - Jan 31 2025
Course Curriculum
1 Subject
E01 Foundation
4 Exercises • 57 Learning Materials
Advanced Digital Design
Overview and Introduction of Analog and Digital Signals
Video
3:13
Module Opening
Video
036
Digital Fundamentals Teaser
ZIP
Module1_Introduction
Video
20:5
Module 2 - Introduction to Number System
Video
14:41
Module 2.1 - Number Based Conversion
Video
35:52
Module 2.2 - Signed and Unsigned Numbers
Video
24:10
Module 2.3 - Binary Airthmetic
Video
30:51
Module 3 - Introduction ( BCD, Excess 3 Code, Gray Code, Binary and Gray Code Conversions)
Video
31:39
Module 3.1 - (Alphanumeric and self detecting codes, Self Complimentary Property)
Video
17:51
Module 4- Introduction( Logic gates, Boolean Theorems, canonical and Standard Forms)
Video
37:10
Module 5 -( Introduction, Map methods, K-Map Rules, AOI Implememtation, Eg)
Video
40:40
Module 6 -( Introduction and Adders)
Video
25:7
Module 6.1 -( Ripple Carry and Carry look Ahead Adder)
Video
20:41
Module 6.2-( Decoder and Encoder)
Video
18:57
Module 6.3 - ( MUX, DMUX, Magnitude Comparator)
Video
26:46
Module 7-(Introduction, Counters, Flip-Flops)
Video
30:51
Module 7.1-(Registers and Latches)
Video
22:22
Practical Applications
Video
6:46
Tools Used in Analog and Digital Signals
Video
4:53
Emerging Trends
Video
5:10
Challenges and Solutions
Video
6:47
Collaborative Activities
PDF
Review and Recap
PDF
Supplementary Material
PDF
Assessment Components
Exercise
Module 8 : Finite State Machines
Video
30:20
Module 8.1 : FSM - Memory Introduction
Video
16:16
Module 8.3 : FSM -RAM
Video
11:22
Module 8.4: FSM - ROM
Video
9:25
Module 8.5 : FSM - PLD
Video
15:14
Supplementary Materials
PDF
FSM
Exercise
Combinational Logic Circuits Teaser
ZIP
Sequential Circuits Teaser
ZIP
Weekly Assignment
PDF
PPT Submission
Assignment
Digital Design using Verilog - 1
Overview and Introduction
application/octet-stream
Module Opening
Video
1:32
Digital Design using Verilog
Video
49:23
Verilog Introduction
Video
12:8
Digital Design using Verilog
Video
40:50
Digital Design using Verilog
Video
42:5
Digital Design using Verilog
Video
45:46
Digital Design using Verilog
Video
39:43
Challenges and Solutions
PPT
Emerging Trends
Video
30:39
Supplementary materials
application/vnd.openxmlformats-officedocument.wordprocessingml.documentapplication/vnd.openxmlformats-officedocument.wordprocess
Quiz
Exercise
Capstone Project using Verilog
Capstone projects
PDF
Capstone projects
PDF
Capstone projects
Video
17:40
Capstone projects
Video
22:52
Capstone projects
Video
10:53
Capstone projects
Video
21:42
Capstone projects
Video
15:58
Capstone projects
Video
24:37
Capstone projects
Video
18:3
Capstone projects
Video
16:10
Capstone projects
PDF
Capstone projects
Video
44:18
Course Instructor
Meghana
13 Courses • 640 Students
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