Physical Design - PD50
Physical Design has evolved as a complex specialization in VLSI and an in-demand skill for the last 2 decades. VLSI Design cycle involves preparing the design for fabrication at a selected foundry (TSMC, Global Foundries, SAMSUNG ..), with a specific technology node (10nm, 7nm..). This process involves several steps including Synthesis, floor plan, power plan, placement, clock tree synthesis, routing, static timing analysis, and Timing optimization, and ends with delivering GDSII files to the foundry after doing all sign-off checks.
FREE
/CourseBundles(54696)/3814308-freepik--20250219104043u6A3.jpeg)
Course Overview
Schedule of Classes
Start Date & End Date
May 14 2025 - May 31 2025
Course Curriculum
2 Subjects
Physical Design
2 Exercises • 2 Learning Materials
Course Orienation Slides - PD50
Orientation Slide
Course Planner - PD50
Course planner - PD50
Intermediate Assessment
Intermediate Assessment - 1
Intermediate Assessment - 2
Intermediate Assessment 2
PDLRM
83 Learning Materials
Digital Design
Digital Design Slides
CMOS Devices and Technology
CMOS Devices and Technology Slides
Verilog HDL
Verilog HDL Slides
Linux Essentials
Linux Essentials Slides
TCL Scripting
TCL Scripting Slides
TCL Scripting Complete
TCL Scripting Updated 2023
Physical Design - Theory
Module 1 CMOS and ASIC Design
Module 2 Synthesis
Module 3 Data Preparation
Module 4 Sanity Checks
Module 5 PD Flow and Terminology
Module 6 Floor plan
Module 7 Power Planning
Module 8 STA 1
Module 9 Placement
Module 10 CTS
Module 2 - Synthesis 1
Module 2 - Synthesis 2
Module 2 - Synthesis 3
Module 11 Routing
Module 12 Optimization Techniques
Module 13 Process Variations
Module 14 Sign Off I
Module 15 Sign Off II
Module 16 Advanced Timing Concepts
Module 17 Introduction to Low Power Design
Physical Design - LAB
Lab Manual 1 Synthesis logical
Lab Manual 2 Synthesis physical
Lab Manual 3 Data preparation
Lab Manual 4 Floorplan
Lab Manual 5 Power plan
Lab Manual 6 Placement
Lab Manual 7 CTS
Lab Manual 8 Routing
Lab Manual 9 Parasitic Extraction
Lab Manual 10 Signoff STA
Lab Manual 11 ECO Flow
Lab Manual 12 Physical Verification
Synopsys Tool Manuals
IC validator user guide
ICC Command Reference
ICC invocation commands
ICC Technology - Routing Rules Manual
ICC user guide
Library preparation guide for ICC
PT user guide
SDC Constraints Appnote
StarRC User Guide
Timing Constraints _ optimization User guide
ICC Articles
ADR_AppNotes_201012_v1-2
Clock-Gating Methodology
cts_checklist_v2
CTS_recommendations_and_debugging
Determining the Exact Net Length
eco_flow_app_note
Examples Describing Interclock Delay Balancing Usage
Fixing Hold Time Violations by Inserting Delay at the Data Path Endpoint
How Are Clock Gating Checks Inferred
How to Control the Cell Name Prefix of New Cells
Identifying Buffers Added During Hold Fixing
IC Compiler Flow With Crosstalk Pevention and Fixing
ICC_CTS_sweet_spot_v12_custom
Incremental Congestion Removal After Clock Tree Synthesis
Interclock Delay Balancing During Clock Tree Synthesis
Interclock Delay Balancing Usage
J-2014 09_CTS_update_training_slides_General_CTS
J-2014 09 PG_Tie off_Editing AN
Physical_IP_Workshop_ARM_CPU_Hardening
Postroute Clock Tree Optimization
PrimeTime SI_s Crosstalk Analysis
Reducing Congestion With IC Compiler
Removing Shorts Over Macros
Restricting Clock Tree Cells
SDC and CTS
Viewing and Reporting Errors Found by the verify_pg_nets Command
What Are the Issues Involving Recalculating Reconverging Clock Paths
Reference Books
Digital Circuit
ICC2ug
Static-Timing-Analysis-for-Nanometer-Designs
Project Document
JBI Architecture Specifications
JBI Project Details
Intraview Questions
Interview Questions
Sample Resume Format
Resume Format
Course Instructor
By clicking on Continue, I accept the Terms & Conditions,
Privacy Policy & Refund Policy