Physical Design - Learning and Reference Materials

Course LRM includes Training PPTs (Foundation Course & PD Course), ChipEdge Lab Manual, Assignments, Synopsys Tool Manuals, Articles, Referance Books, Videos, Interview Questions and Sample Resume etc., Learners will explore the importance of choosing appropriate learning and reference materials and learn effective strategies for utilizing them to enhance their learning experience.

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Course Overview

Schedule of Classes

Course Curriculum

1 Subject

Physical Design - Learning and Reference Materials

69 Learning Materials

Foundation Courses Slides

Digital Design Slides

PDF

CMOS Devices and Technology Slides

PDF

Verilog HDL Slides

PDF

Linux Essentials Basics and GVIM

PDF

TCL Scripting Slides

TCL Scripting Updated 2023

PDF

TCL Scripting Basics

PDF

TCL Scripting Complete

PDF

Physical Design Slides

Module 1 CMOS and ASIC Design

PDF

Module 2 Synthesis

PDF

Module 3 Data Preparation

PDF

Module 4 Sanity Checks

PDF

Module 5 PD Flow and Terminology

PDF

Module 6 Floor plan

PDF

Module 7 Power Planning

PDF

Module 8 STA 1

PDF

Module 9 Placement

PDF

Module 10 CTS

PDF

Physical Design - Lab Manuals

Lab Manual 1 - Synthesis logical

PDF

Lab Manual 2 - Synthesis physical

PDF

Lab Manual 3 - Data preparation

PDF

Lab Manual 4 - Floorplan

PDF

Lab Manual 5 - Powerplan

PDF

Lab Manual 6 - Placement

PDF

Lab Manual 7 - CTS

PDF

Lab Manual 8 - Routing

PDF

Lab Manual 9 - Parasitic Extraction

PDF

Lab Manual 10 - Signoff STA

PDF

Lab Manual 11 - ECO Flow

PDF

Lab Manual 12 - Physical Verification

PDF

Synopsys Tool Manuals

IC validator user guide

PDF

ICC Command Reference

PDF

ICC invocation commands

PDF

ICC Technology - Routing Rules Manual

PDF

ICC user guide

PDF

Library preparation guide for ICC

PDF

PT user guide

PDF

SDC Constraints Appnote

PDF

StarRC User Guide

PDF

Timing Constraints _ optimization User guide

PDF

ICC Articles

ADR_AppNotes_201012_v1-2

PDF

Clock-Gating Methodology

PDF

cts_checklist_v2

PDF

CTS_recommendations_and_debugging

PDF

Determining the Exact Net Length

PDF

eco_flow_app_note

PDF

Examples Describing Interclock Delay Balancing Usage

PDF

Fixing Hold Time Violations by Inserting Delay at the Data Path Endpoint

PDF

How Are Clock Gating Checks Inferred

PDF

How to Control the Cell Name Prefix of New Cells

PDF

IC Compiler Flow With Crosstalk Pevention and Fixing

PDF

Identifying Buffers Added During Hold Fixing

PDF

ICC_CTS_sweet_spot_v12_custom

PDF

Incremental Congestion Removal After Clock Tree Synthesis

PDF

Interclock Delay Balancing During Clock Tree Synthesis

PDF

Interclock Delay Balancing Usage

PDF

J-2014 09_CTS_update_training_slides_General_CTS

PDF

J-2014 09 PG_Tie off_Editing AN

PDF

Physical_IP_Workshop_ARM_CPU_Hardening

PDF

Postroute Clock Tree Optimization

PDF

PrimeTime SI_s Crosstalk Analysis

PDF

Reducing Congestion With IC Compiler

PDF

Removing Shorts Over Macros

PDF

Restricting Clock Tree Cells

PDF

SDC and CTS

PDF

Viewing and Reporting Errors Found by the verify_pg_nets Command

PDF

What Are the Issues Involving Recalculating Reconverging Clock Paths

PDF

Reference Books

Digital Circuit

PDF

ICC2ug

PDF

Static-Timing-Analysis-for-Nanometer-Designs

PDF