Key Highlights:

• Understand the basics of RTL design and its significance in the chip design process
• Learn about the GDS-II format and its relevance in IC fabrication
• Explore the different stages of the physical design flow and their interdependencies
• Master the art of floorplanning, power planning, placement, and routing to achieve optimal chip performance
• Perform timing optimization to meet design constraints
• Conduct thorough signoff checks to ensure design integrity and manufacturability
• Hands-on experience with industry-standard EDA tools commonly used in physical design

What you will learn:

• RTL Design
  Understand the basics of RTL design and its importance in the physical design flow.
• GDS-II Format
  Learn about the GDS-II format and its role in the fabrication of integrated circuits.
• Physical Design Flow
  Explore the entire physical design flow, including synthesis, floorplanning, placement, routing, timing optimization, power planning, and signoff checks.
• Floorplanning and Placement
  Master the techniques of floorplanning and placement to achieve optimal chip performance.
• Routing and Timing Optimization
  Learn about routing techniques and perform timing optimization to meet design constraints.
• Power Planning
  Understand the importance of power planning in chip design and learn various power planning techniques.
• Signoff Checks
  Conduct thorough signoff checks to ensure design integrity and manufacturability.