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Place and Route ( Netlist to GDSII Design Flow)

Place and Route (Netlist to GDS-II Design Flow) is a comprehensive course that teaches the process of converting a netlist into a physical layout using industry-standard tools. This course covers the entire design flow, from the initial placement of gates and macros to the final routing of interconnects. Students will gain a deep understanding of the different algorithms and techniques involved in achieving optimal placement and efficient routing. Key Highlights: In-depth coverage of place and route techniques Hands-on experience with industry-standard tools Optimization strategies for achieving high-quality layouts Understanding the impact of various design constraints What you will learn: Netlist to Placement: This module focuses on the initial placement of gates and macros using advanced algorithms. Students will learn how to optimize for area, wirelength, delay, and other metrics. Techniques for handling various design constraints will also be discussed. Placement to Routing: In this module, students will learn how to convert the placement solution into a routing solution. Topics include global and detailed routing, congestion estimation, routing congestion-driven placement, and more. Post-Route Optimization: Here, students will explore techniques for improving the final routing solution. Topics covered include clock tree synthesis, power optimization, shielding, buffering, and design rule checks. Final Steps: In this module, students will learn about the remaining steps in the design flow, such as parasitic extraction, timing analysis, and validation of the final layout. Students will gain the necessary skills to prepare the design for manufacturing.

Course Instructor: ChipEdge Learning

₹21600.00

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Course Overview

Key Highlights:

  • In-depth coverage of place and route techniques
  • Hands-on experience with industry-standard tools
  • Optimization strategies for achieving high-quality layouts
  • Understanding the impact of various design constraints

What you will learn:

  • Netlist to Placement:
    This module focuses on the initial placement of gates and macros using advanced algorithms. Students will learn how to optimize for area, wirelength, delay, and other metrics. Techniques for handling various design constraints will also be discussed.
  • Placement to Routing:
    In this module, students will learn how to convert the placement solution into a routing solution. Topics include global and detailed routing, congestion estimation, routing congestion-driven placement, and more.
  • Post-Route Optimization:
    Here, students will explore techniques for improving the final routing solution. Topics covered include clock tree synthesis, power optimization, shielding, buffering, and design rule checks.
  • Final Steps:
    In this module, students will learn about the remaining steps in the design flow, such as parasitic extraction, timing analysis, and validation of the final layout. Students will gain the necessary skills to prepare the design for manufacturing.

Schedule of Classes

Course Curriculum

1 Subject

Place and Route ( Netlist to GDSII Design Flow)

9 Exercises • 72 Learning Materials

CMOS & ASIC Design

Introduction to CMOS​

Video
01:53:45

Technology Nodes & Trends

Video
00:14:54

ASIC Design : Ecosystem

Video
01:10:13

Design Specification

Video
00:05:28

Synthesis

Video
00:16:25

Physical Design Flow

Video
00:20:00

Post GDS

Video
00:03:47

Assignment

PDF

Quiz

Exercise

Data Preparation

Inputs To Block PD Implementation

Video
00:13:56

Files Required for PD Implementation

Video
00:56:33

Additional Information

Video
00:03:01

Assignment

PDF

Quiz

Exercise

Sanity Checks

Introduction to Sanity Checks

Video
00:09:35

Netlist Check

Video
00:25:23

SDC Checks

Video
00:07:54

Library Checks

Video
00:03:28

Assignment

PDF

Quiz

Exercise

PD Flow and Terminology

Full Chip Partitioning

Video
01:00:55

Powerplan

Video
00:11:30

Placement & Optimization

Video
00:26:08

CTS & Optimization

Video
00:18:35

Routing & Optimization

Video
00:05:08

Signoff

Video
00:13:08

Floorplanning

Introduction to Floor Planning

Video
00:29:30

Deciding the Size of the Block

Video
00:54:02

Deciding the Shape of the Block

Video
00:21:54

I/O Port Placement

Video
00:13:08

Macro Placement

Video
01:08:57

Physical only Cells

Video
00:31:39

Floorplan Checklist

Video
00:04:28

Types of SoC Floorplan

Video
00:11:14

Flat and Hierarchical Floorplanning

Video
00:14:48

Additional Information

Video
00:06:05

Assignment

PDF

Quiz

Exercise

Powerplanning

Power Plan Objectives

Video
00:11:13

Power Consumption in IC

Video
00:26:47

Power Planning

Video
00:56:40

Low Power Techniques

Video
00:33:19

Assignment

PDF

Quiz

Exercise

STA-1

Introduction to STA-1

Video
00:53:41

Setup

Video
00:11:20

Hold

Video
00:08:28

Timing Reports

Video
00:13:02

Timing Checks-Setup & Hold

Video
00:46:36

Clock Skew

Video
00:51:12

Additional Information

Video
00:04:23

Assignment

PDF

Quiz

Exercise

Placements

Introduction To Placement

Video
00:11:13

Physical Cells

Video
00:37:28

Placement Methodologies

Video
00:09:32

Steps During Placement

Video
00:24:34

Post Placement

Video
00:05:07

Scan Chain

Video
00:21:39

QoR Analysis

Video
00:05:24

Congestion Analysis

Video
00:44:09

Timing Analysis

Video
00:11:36

Placement Checks

Video
00:06:15

Assignment

PDF

Quiz

Exercise

Clock Tree Synthesis CTS

Introduction To CTS

Video
00:28:36

CTS Specifications

Video
00:28:28

CTS QoR

Video
00:05:39

Clock Uncertainty

Video
00:34:07

CTS & Opt-Quality Checks

Video
00:09:03

Additional Topics

Video
00:13:58

Assignment

PDF

Quiz

Exercise

Routing

Introduction To Routing

Video
00:31:36

Routing Flow

Video
00:23:42

Post Route Optimization

Video
00:12:11

Cross Talk

Video
00:32:52

Antenna Violation

Video
00:34:06

Routing Quality Summary

Video
00:09:14

Assignment

PDF

Quiz

Exercise

Course Instructor

tutor image

ChipEdge Learning

98 Courses   •   900 Students