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Scan Insertion & Scan Compression with OCC

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

Course Instructor: ChipEdge Learning

₹7500.00

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Course Overview

Scan Insertion without Compression:

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

 This course talks about detailed concepts on Scan Insertion, and Scan Design Rules with suitable examples. This course will give in-depth details on Lockup Latches.

Scan Insertion and Scan Compression with OCC:

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

 This course talks about detailed concepts on Scan Insertion, and Scan Design Rules with suitable examples. This course will give in-depth details on Lockup Latches.

You will also learn how to reduce the test application time, test data volume, and thereby test cost of an IC due to the increase in size and complexity with the concept of scan compression. The concepts of OCC is also discussed in this course.

Schedule of Classes

Course Curriculum

1 Subject

Scan Insertion & Scan Compression with OCC

3 Exercises • 34 Learning Materials

Introduction to DFT

Introduction to SOC

Video
00:25:45

DFT Basics

Video
00:40:52

Chip Fabrication Process

Video
00:31:25

Quiz

Exercise

Assignment

PDF

Lab Guide

PDF

Introduction to Scan Insertion

Video
01:27:52

Scan Insertion

Scan Architecture Overview

Video
00:49:08

Scan Design Basics

Video
00:55:50

Scan Golden Rules

Video
00:57:01

ICG and Lockup Latches

Video
00:22:21

Test Protocol DRC

Video
00:25:05

Quiz

Exercise

Assignment

PDF

Lab Guide

PDF

Tool Invoke

Video
01:13:31

Lab Guide

PDF

DRC Violation and Fix_DC Commands

Video
01:56:45

Lab Guide

PDF

DRC Violation and Fix_Netlist Hack

Video
00:41:48

Lab Guide

PDF

Multi Chain Scan Insertion

Video
01:05:46

Scan Compression

Need for Scan Compression

Video
00:22:57

Scan Compression Architecture

Video
00:45:28

Scan Compression Modes

Video
00:10:20

Hierachical Scan Design, At-speed and OCC

Video
00:25:37

Quiz

Exercise

Assignment

PDF

Lab Guide

PDF

Compression Lab

Video
01:12:13

Lab Guide

PDF

Compression Ratio Max Chain

Video
00:47:12

CTL File Part-1

Video
00:29:19

CTL File Part-2

Video
01:03:14

Lab Guide

PDF

OCC Insertion

Video
01:24:36

Lab Guide

PDF

Course Instructor

tutor image

ChipEdge Learning

98 Courses   •   900 Students