Key Highlights:

• Learn the fundamentals of synthesis, signoff STA, and LEC
• Understand the usage of Synopsys Tools
• Explore the various stages involved in synthesis and signoff STA
• Master the techniques for logic equivalence checking
• Hands-on lab exercises for practical implementation

What you will learn:

• Synthesis:
  Gain knowledge about the synthesis process and learn how to optimize a design using Synopsys synthesis tools.
• Signoff STA:
  Understand the significance of signoff STA and learn the techniques to meet timing constraints using Synopsys static timing analysis tools.
• Logic Equivalence Checking (LEC):
  Learn the methods for verifying the equivalence of two different representations of a circuit and master the use of Synopsys LEC tools.