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Synthesis using Design Compiler (Synopsys Tools)

Synthesis using Design Compiler is a comprehensive course that teaches how to effectively use the Synopsys Tools for logic synthesis. This course provides hands-on experience with the Design Compiler tool, which is widely used for transforming RTL (Register Transfer Level) designs into synthesized gate-level representations. It covers fundamental concepts and advanced techniques required to optimize and improve the design qualities for digital integrated circuits.

Course Instructor: ChipEdge Learning

₹40969.00

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Course Overview

Key Highlights:

  • Coverage of Design Compiler basics and advanced features
  • Understanding synthesis constraints and optimization techniques
  • Hands-on experience with real-world examples and case studies
  • Best practices for efficient and effective synthesis flows

What you will learn:

  • Synthesis basics and RTL coding guidelines
    Learn the fundamentals of synthesis and the recommended coding styles for optimal synthesis results.
  • Design Compiler user interface and commands
    Explore the various commands and features of the Design Compiler tool and understand its user interface.
  • Advanced synthesis techniques and optimization methods
    Discover advanced techniques such as retiming, restructuring, and power optimization to enhance the design quality.
  • Synthesis constraints and methodologies
    Master the usage of constraints to guide the synthesis process and achieve specific design goals.
  • Performance analysis and optimization
    Learn how to analyze and optimize the performance of synthesized designs.

Schedule of Classes

Course Curriculum

1 Subject

Synthesis using Design Compiler (Synopsys Tools)

24 Learning Materials

Synthesis Overview & Timing Structures

Synthesis Overview & Flow

Video
01:24:24

Designing Structures & Timing Analysis

Video
01:40:04

Lecture Slides

PDF

Lab Manual

PDF

Lab Part I

Video
01:06:27

Lab Part II

Video
01:24:49

Constraining the Design

Creating CLOCK & Attributes

Video
01:26:45

Reporting & Analyzation

Video
02:01:32

Lecture Slides

PDF

Lab Manual

PDF

Lab Part I

Video
01:41:17

Lab Part II

Video
00:04:34

RTL Coding Guidelines & SCAN Insertion

Statements & Flip-Flop

Video
01:19:33

SCAN Insertion & DFT Flow

Video
01:38:52

Lecture Slides

PDF

Lab Manual

PDF

Lab Part I

Video
01:37:54

Lab Part II

Video
01:39:47

Low Power Synthesis

Low Power Synthesis -Overview

Video
01:22:09

UPF & Flow Diagram

Video
00:35:03

Lecture Slides

PDF

Lab Manual

PDF

Lab Part I

Video
01:16:19

Lab Part II

Video
01:37:30

Course Instructor

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ChipEdge Learning

98 Courses   •   900 Students